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general description the max1146?ax1149 low-power, 14-bit, multichan- nel, analog-to-digital converters (adcs) feature an internal track/hold (t/h), voltage reference, and clock. the max1146/max1148 operate from a single +4.75v to +5.25v supply, and the max1147/max1149 operate from a single +2.7v to +3.6v supply. all analog inputs are software configurable for unipolar/bipolar and sin- gle-ended/differential operation. the 4-wire serial interface connects directly to spi/qspi/microwire devices without external logic. the serial strobe output (sstrb) allows conve- nient connection to digital signal processors. the max1146?ax1149 use an internal clock or an exter- nal serial-interface clock to perform successive-approx- imation analog-to-digital conversions. the max1146/max1148 include an internal +4.096v reference, while the max1147/max1149 include an internal +2.500v reference. all devices accept an exter- nal reference from 1.5v to v dd . the max1146?ax1149 provide a hardware shutdown and two software power-down modes. using the soft- ware power-down modes allows the devices to be pow- ered down between conversions. when powered down, accessing the serial interface automatically powers up the devices. the quick turn-on time allows power-down between all conversions. this technique reduces sup- ply current to under 120? for quick turn-on. the max1146?ax1149 are available in a 20-pin tssop package. applications portable data logging data acquisition medical instruments battery-powered instruments process control features ? 8-channel single-ended or 4-channel differential inputs (max1148/max1149) ? 4-channel single-ended or 2-channel differential inputs (max1146/max1147) ? internal multiplexer and t/h ? single-supply operation 4.75v to 5.25v supply (max1146/max1148) 2.7v to 3.6v supply (max1147/max1149) ? internal reference +4.096v (max1146/max1148) +2.500v (max1147/max1149) ? 116ksps sampling rate ? low power 1.1ma (116ksps) 120? (10ksps) 12? (1ksps) 300na (power-down mode) ? spi-/qspi-/microwire compatible ? 20-pin tssop max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs ________________________________________________________________ maxim integrated products 1 ordering information/selector guide 19-3488; rev 2; 1/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package inl (lsb) input channels internal reference (v) pkg code max1146 bcup 0 c to +70 c 20 tssop ? 4 +4.096 u20-3 max1146beup -40 c to +85 c 20 tssop ? 4 +4.096 u20-3 max1147 bcup 0 c to +70 c 20 tssop ? 4 +2.500 u20-3 max1147beup -40 c to +85 c 20 tssop ? 4 +2.500 u20-3 max1148 bcup 0 c to +70 c 20 tssop ? 8 +4.096 u20-3 max1148beup -40 c to +85 c 20 tssop ? 8 +4.096 u20-3 max1149 bcup 0 c to +70 c 20 tssop ? 8 +2.500 u20-3 max1149beup -40 c to +85 c 20 tssop ? 8 +2.500 u20-3 spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. pin configurations appear at end of data sheet.
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 5v (max1146/max1148), v dd = 3.3v (max1147/max1149), shdn = v dd , v com = 0, f sclk = 2.1mhz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), v refadj = v dd , c ref = 2.2?, external +4.096v reference at ref (max1146/ max1148), external 2.500v reference at ref (max1147/max1149), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd, dgnd ............................................-0.3v to +6.0v agnd to dgnd.....................................................-0.3v to +0.3v ch0?h7, com to agnd..........................-0.3v to (v dd + 0.3v) ref, refadj to agnd ..............................-0.3v to (v dd + 0.3v) digital inputs to dgnd...............................-0.3v to (v dd + 0.3v) digital outputs to dgnd ............................-0.3v to (v dd + 0.3v) digital output sink current .................................................25ma continuous power dissipation (t a = +70?) 20 tssop (derate 10.9mw/? above +70?) .............879mw operating temperature ranges max114_ bc_ _ ..................................................0? to +70? max114_ be_ _ ...............................................-40? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy (note 1) resolution 14 bits relative accuracy (note 2) inl ?.7 ? lsb differential nonlinearity dnl no missing codes over temperature -1.0 ?.5 +1.5 lsb offset error ?0 lsb offset temperature coefficient 0.3 ppm/? gain error (note 3) ?0 lsb gain temperature coefficient ?.8 ppm/? channel-to-channel offset matching ? lsb channel-to-channel gain matching ? lsb dynamic specifications (1khz sine-wave input, 2.5v p-p , full-scale analog input, 116ksps, 2.1mhz external clock) signal-to-noise plus distortion ratio sinad 77 81 db total harmonic distortion thd up to the 5th harmonic -96 -88 db spurious-free dynamic range sfdr 84 98 db channel-to-channel crosstalk (note 4) -85 db small-signal bandwidth ssbw -3db point 3.0 mhz full-power bandwidth fpbw sinad > 68db 2.0 mhz conversion rate external clock, 2.1mhz 15 sclk cycles 7.2 conversion time (note 5) t conv internal clock 6 8 ?
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 5v (max1146/max1148), v dd = 3.3v (max1147/max1149), shdn = v dd , v com = 0, f sclk = 2.1mhz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), v refadj = v dd , c ref = 2.2?, external +4.096v reference at ref (max1146/ max1148), external 2.500v reference at ref (max1147/max1149), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units 18 clocks/conversion 60.3 internal clock mode, f sclk = 2.1mhz 24 clocks/conversion 51.5 18 clocks/conversion 116.66 throughput rate f sample external clock mode, f sclk = 2.1mhz 24 clocks/conversion 87.50 ksps t/h acquisition time t acq 1.4 ? aperture delay t ad 20 ns aperture jitter t aj <50 ps external clock mode 0.1 2.1 serial clock frequency f sclk internal clock mode 0 2.1 mhz internal clock frequency 2.1 mhz analog inputs (ch0?h7, com) unipolar, com = 0 0 v ref input voltage range, single- ended and differential (note 6) bipolar, com = v ref / 2, single-ended ? ref / 2 v multiplexer leakage current on/off-leakage current, v ch _ = 0 to v dd ?.01 ? ? input capacitance 18 pf internal reference (c ref = 2.2?, c refadj = 0.01?) max1147/max1149, t a = +25? 2.480 2.500 2.520 ref output voltage v ref max1146/max1148, t a = +25? 4.076 4.096 4.116 v ref short-circuit current i refsc ref = dgnd 20 ma max114_ bc _ _ ?0 ?0 v ref tempco (note 7) max114_ be _ _ ?0 ?0 ppm/? load regulation 0 to 0.2ma output load (note 8) 2.0 mv capacitive bypass at ref 2f capacitive bypass at refadj 0.01 ? refadj output voltage 1.250 v refadj input range ?8 mv refadj logic high pull refadj high to disable the internal bandgap reference and reference buffer v dd - 0.25v v max1147/max1149 2.000 reference buffer voltage gain max1146/max1148 3.277 v/v
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 5v (max1146/max1148), v dd = 3.3v (max1147/max1149), shdn = v dd , v com = 0, f sclk = 2.1mhz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), v refadj = v dd , c ref = 2.2?, external +4.096v reference at ref (max1146/ max1148), external 2.500v reference at ref (max1147/max1149), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units external reference at ref ref input voltage range v ref 1.5 v dd + 50mv v 125 450 ref input current i ref shutdown 0.01 10 ? ref input resistance 68 k ? digital inputs (din, sclk, cs , shdn ) v dd < 3.6v 2.0 input high voltage v ih v dd > 3.6v 3.0 v input low voltage v il 0.8 v input hysteresis v hyst 0.2 v input leakage i in ? ? input capacitance c in 10 pf digital output (dout, sstrb) output-voltage low v ol i sink = 2ma 0.4 v output-voltage high v oh i source = 2ma v dd - 0.5 v tri-state leakage current i l cs = v dd ?0 ? tri-state output capacitance c out cs = v dd 10 pf power requirements max1147/max1149 2.7 3.6 positive supply voltage v dd max1146/max1148 4.75 5.25 v 116ksps 1.1 1.5 10ksps 0.12 external reference 1ksps 0.012 ma supply current (note 8) i dd normal operation, full- scale input internal reference at 116ksps 1.9 2.4 ma fast power-down 120 full power-down 0.3 shutdown supply current (note 8) shdn = dgnd 0.3 10 ? power-supply rejection (note 9) psr external reference ?.2 mv
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs _______________________________________________________________________________________ 5 note 1: tested at v dd = 3.0v (max1147/max1149) or 5.0v(max1146/max1148); v com = 0; unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 3: offset nulled. measured with external reference. note 4: ?n?channel grounded; full-scale 1khz sine wave applied to all ?ff?channels. note 5: conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (see figures 8?1.) note 6: the common-mode range for the analog inputs is from agnd to v dd . note 7: digital inputs equal v dd or dgnd. note 8: external load should not change during conversion for specified accuracy. note 9: measured as (v fs x 3.6v) - (v fs x 2.7v) for the max1147/max1149 and (v fs x 5.25v) - (v fs x 4.75v) for the max1146/max1148. v dd = 3.6v to 2.7v for max1147/max1149 and v dd = 5.25v to 4.75v for the max1146/max1148. timing characteristics (v dd = 4.75v to 5.25v (max1146/max1148), v dd = 2.7v to 3.6v (max1147/max1149), shdn = v dd , v com = 0, f sclk = 2.1mhz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), v refadj = v dd , c ref = 2.2?, external +4.096v reference at ref for the max1146/max1148, external 2.500v reference at ref for the max1147/max1149, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (figures 1, 2, and 3) parameter symbol conditions min typ max units din to sclk setup time t ds 50 ns din to sclk hold time t dh 0ns sclk fall to output data valid t dov c load = 50pf 10 80 ns cs fall to dout enable t doe c load = 50pf 120 ns cs rise to dout disable t dod c load = 50pf 120 ns shdn rise cs fall to sclk rise time t css 50 ns shdn rise cs fall to sclk rise hold time t csh 50 ns external clock mode 0.1 2.1 sclk clock frequency f sclk internal clock mode 0 2.1 mhz sclk pulse-width high t ch internal clock mode 100 ns sclk pulse-width low t cl internal clock mode 100 ns cs fall to sstrb output enable t ste external clock mode only 120 ns cs rise to sstrb output disable t std external clock mode only 120 ns sstrb rise to sclk rise t sck internal clock mode only 0 ns sclk fall to sstrb edge t scst 80 ns cs pulse width t csw 100 ns
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 6 _______________________________________________________________________________________ v dd dgnd dout 6k ? c load 50pf dgnd 6k ? dout c load 50pf dgnd a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol figure 1. load circuits for enable time v dd dgnd dout 6k ? c load 50pf dgnd 6k ? dout c load 50pf dgnd a) v oh to high-z b) v ol to high-z figure 2. load circuits for disable time high-z sclk din start sel2 sel1 sel0 pd1 pd0 189 t acq sstrb (internal clock mode) sstrb (external clock mode) dout d13 d12 d11 d10 high-z t csh t ch t cl t css t ds t dh 1 f sclk t doe t ste t dov 24 d2 d1 d0 t dod t std t csw high-z high-z t sck t scst t scst cs sgl/dif uni/bip figure 3. detailed operating characteristics
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs _______________________________________________________________________________________ 7 inl vs. output code max1146 toc01 output code inl (lsb) 12288 8192 4096 -1.0 -0.5 0 0.5 1.0 1.5 -1.5 0 16384 dnl vs. output code max1146 toc02 output code dnl (lsb) 12288 8192 4096 -1.0 -0.5 0 0.5 1.0 1.5 -1.5 0 16384 supply current vs. supply voltage (max1147/max1149) max1146 toc03 supply voltage (v) supply current (ma) 3.3 3.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 2.7 3.6 internal reference external reference supply current vs. supply voltage (max1146/max1148) max1146 toc04 supply voltage (v) supply current (ma) 5.20 5.15 5.05 5.10 4.85 4.90 4.95 5.00 4.80 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 4.75 5.25 internal reference external reference shutdown supply current vs. supply voltage (max1147/max1149) max1146 toc05 supply voltage (v) shutdown supply current ( a) 3.5 3.4 3.2 3.3 2.9 3.0 3.1 2.8 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2.7 3.6 supply current vs. conversion rate max1146 toc07 conversion rate (ksps) supply current ( a) 100 10 1 0.1 200 400 600 800 1000 1200 0 0.01 1000 fast power-down full power-down supply current vs. temperature max1146 toc08 temperature ( c) supply current (ma) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 0 -40 85 max1146/max1148 internal reference max1147/max1149 internal reference max1146/max1148 external reference max1147/max1149 external reference shutdown supply current vs. temperature max1146 toc09 temperature ( c) shutdown supply current ( a) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 -40 85 max1146/max1148 max1147/max1149 typical operating characteristics (v dd = +5.0v (max1146/max1148), v dd = +3.3v (max1147/max1149), shdn = v dd , v com = 0, f sclk = 2.1mhz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), v refadj = v dd , external +4.096v reference at ref (max1146/max1148), exter- nal +2.500v reference at ref (max1147/max1149), c ref = 2.2?, c load = 50pf, t a = +25?, unless otherwise noted.) shutdown supply current vs. supply voltage (max1146/max1148) max1146 toc06 supply voltage (v) shutdown supply current ( a) 5.15 5.05 4.95 4.85 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0 4.75 5.25
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 8 _______________________________________________________________________________________ reference voltage vs. supply voltage (max1146/max1148) max1146 toc10 supply voltage (v) reference voltage (v) 5.15 5.05 4.85 4.95 4.0945 4.0950 4.0955 4.0960 4.0965 4.0970 4.0975 4.0980 4.0940 4.75 5.25 reference voltage vs. supply voltage (max1147/max1149) max1146 toc11 supply voltage (v) reference voltage (v) 3.3 3.0 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 2.4980 2.7 3.6 reference voltage vs. temperature (max1146/max1148) max1146 toc12 temperature ( c) reference voltage (v) 60 35 10 -15 4.091 4.092 4.093 4.094 4.095 4.096 4.097 4.098 4.099 4.100 4.090 -40 85 reference voltage vs. temperature (max1147/max1149) max1146 toc13 temperature ( c) reference voltage (v) 60 35 10 -15 2.498 2.499 2.500 2.501 2.502 2.503 2.497 -40 85 reference buffer power-up delay vs. time in shutdown max1146 toc14 time in shutdown (s) delay ( s) 1 0.1 0.01 500 1000 1500 2000 2500 0 0.001 10 c ref = 4.7 f c refadj = 0.01 f fft plot max1146 toc15 frequency (hz) amplitude (db) 5000 4000 3000 2000 1000 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 -120 0 f in = 1khz f sample = 116ksps v dd = 5v/3v effective number of bits vs. frequency max1146 toc16 frequency (khz) effective number of bits 46 37 28 19 10 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 13.0 12.0 155 typical operating characteristics (continued) (v dd = +5.0v (max1146/max1148), v dd = +3.3v (max1147/max1149), shdn = v dd , v com = 0, f sclk = 2.1mhz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), v refadj = v dd , external +4.096v reference at ref (max1146/max1148), exter- nal +2.500v reference at ref (max1147/max1149), c ref = 2.2?, c load = 50pf, t a = +25?, unless otherwise noted.)
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs _______________________________________________________________________________________ 9 gain error vs. supply voltage (max1147/max1149) max1146 toc19 supply voltage (v) gain error (lsb) 3.3 3.0 -4 -2 0 2 4 6 -6 2.7 3.6 gain error vs. supply voltage (max1146/max1148) max1146 toc20 supply voltage (v) gain error (lsb) 5.15 5.05 4.85 4.95 -4 -2 0 2 4 6 -6 4.75 5.25 channel-to-channel gain matching vs. supply voltage (max1147/max1149) max1146 toc21 supply voltage (v) gain matching (lsb) 3.3 3.0 -4 -2 0 2 4 6 -6 2.7 3.6 channel-to-channel gain matching vs. supply voltage (max1146/max1148) xmax1146 toc22 supply voltage (v) gain matching (lsb) 5.15 5.05 4.95 4.85 -4 -2 0 2 4 6 -6 4.75 5.25 typical operating characteristics (continued) (v dd = +5.0v (max1146/max1148), v dd = +3.3v (max1147/max1149), shdn = v dd , v com = 0, f sclk = 2.1mhz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), v refadj = v dd , external +4.096v reference at ref (max1146/max1148), exter- nal +2.500v reference at ref (max1147/max1149), c ref = 2.2?, c load = 50pf, t a = +25?, unless otherwise noted.) offset error vs. supply voltage (max1147/max1149) max1146 toc17 supply voltage (v) offset error (lsb) 3.3 3.0 -4 -2 0 2 4 6 -6 2.7 3.6 offset error vs. supply voltage (max1146/max1148) max1146 toc18 supply voltage (v) offset error (lsb) 5.15 5.05 4.95 4.85 -7 -4 -5 -6 -2 -3 -1 0 -8 4.75 5.25
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 10 ______________________________________________________________________________________ offset error vs. temperature max1146 toc28 temperature ( c) offset error (lsb) 60 35 -15 10 -4 -2 0 2 4 6 -6 -40 85 typical operating characteristics (continued) (v dd = +5.0v (max1146/max1148), v dd = +3.3v (max1147/max1149), shdn = v dd , v com = 0, f sclk = 2.1mhz, external clock (50% duty cycle), 18 clocks/conversion (116ksps), v refadj = v dd , external +4.096v reference at ref (max1146/max1148), exter- nal +2.500v reference at ref (max1147/max1149), c ref = 2.2?, c load = 50pf, t a = +25?, unless otherwise noted.) channel-to-channel offset matching vs. temperature max1146 toc26 temperature ( c) offset matching (lsb) 60 35 -15 10 -4 -2 0 2 4 6 -6 -40 85 gain error vs. temperature max1146 toc27 temperature ( c) gain error (lsb) 60 35 -15 10 -4 -2 0 2 4 6 -6 -40 85 channel-to-channel offset matching vs. supply voltage (max1147/max1149) max1146 toc24 supply voltage (v) offset matching (lsb) 3.3 3.0 -4 -2 0 2 4 6 -6 2.7 3.6 channel-to-channel offset matching vs. supply voltage (max1146/max1148) max1146 toc25 supply voltage (v) offset matching (lsb) 5.15 5.05 4.85 4.95 -4 -2 0 2 4 6 -6 4.75 5.25 channel-to-channel gain matching vs. temperature max1146 toc23 temperature ( c) gain matching (lsb) 60 35 -15 10 -4 -2 0 2 4 6 -6 -40 85
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs ______________________________________________________________________________________ 11 pin max1148 max1149 max1146 max1147 name function 1 1 ch0 2 2 ch1 3 3 ch2 4 4 ch3 5 ch4 6 ch5 7 ch6 8 ch7 analog inputs 9 9 com common input. negative analog input in single-ended mode. com sets zero-code voltage in unipolar and bipolar mode. 10 10 shdn active-low shutdown input. pulling shdn low shuts down the device reducing supply current to 0.2?. driving shutdown high enables the devices. 11 11 ref reference-buffer output/adc reference input. reference voltage for analog-to-digital conversion. in internal reference mode, the max1146/max1148 v ref is +4.096v, and the max1147/max1149 v ref is +2.500v. 12 12 refadj bandgap reference output and reference buffer input. bypass to agnd with a 0.01? capacitor. connect refadj to v dd to disable the internal bandgap reference and reference- buffer amplifier. 13 13 agnd analog ground 14 14 dgnd digital ground 15 15 dout serial data output. data is clocked out at the falling edge of sclk when cs is low. dout is high impedance when cs is high. 16 16 sstrb serial strobe output. in internal clock mode, sstrb goes low when the adc conversion begins, and goes high when the conversion is finished. in external clock mode, sstrb pulses high for two clock periods before the msb decision. sstrb is high impedance when cs is high (external clock mode). 17 17 din serial data input. data is clocked in at the rising edge of sclk when cs is low. din is high impedance when cs is high. 18 18 cs active-low chip select. data is not clocked into din unless cs is low. when cs is high, dout is high impedance. 19 19 sclk serial clock input. clocks data in and out of the serial interface and sets the conversion speed in external clock mode. (duty cycle must be 40% to 60%.) 20 20 v dd positive supply voltage. bypass to agnd with a 0.1? capacitor. 5? n.c. no connection. not internally connected. pin description
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 12 ______________________________________________________________________________________ detailed description the max1146?ax1149 adcs use a successive- approximation conversion technique and input t/h cir- cuitry to convert an analog signal to a 14-bit digital output. a flexible serial interface provides easy inter- face to microprocessors (?s). figure 4 shows the typi- cal application circuit and figure 5 shows a functional diagram of the max1148/max1149. true-differential analog input and track/hold the max1146?ax1149 analog input architecture con- tains an analog input multiplexer (mux), two t/h capacitors, t/h switches, a comparator, and two switched capacitor digital-to-analog converters (dacs) (figure 6). in single-ended mode, the analog input mux connects in+ to the selected input channel and in- to com. in differential mode, in+ and in- are connected to the selected analog input pairs such as ch0/ch1. select the analog input channels according to tables 1?. the analog input multiplexer switches to the selected channel on the control byte? fifth sclk falling edge. at this time, the t/h switches are in the track position and c t/h+ and c t/h- track the analog input signal. at the control byte? eighth sclk falling edge, the mux opens and the t/h switches move to the hold position, retain- ing the charge on c t/h+ and c t/h- as a sample of the input signal. see figures 8?1 for input mux and t/h switch positioning. during the conversion interval, the switched capacitive dac adjusts to restore the comparator-input voltage to 0 within the limits of 14-bit resolution. this action requires 15 conversion clock cycles and is equivalent to transferring a charge of 18pf (v in+ - v in- ) from c t/h+ and c t/h- to the binary-weighted capacitive dac, forming a digital representation of the analog input signal. after conversion, the t/h switches move from the hold position to the track position and the mux switches back to the last specified position. in internal clock mode, the conversion is complete on the rising edge of sstrb. in external clock mode, the conversion is com- plete on the eighteenth sclk falling edge. the time required for the t/h to acquire an input signal is a function of the analog input source impedance. if the input signal source impedance is high, the acquisi- tion time lengthens. the max1146?ax1149 provide three sclk cycles (t acq ) in which the t/h capacitance must acquire a charge representing the input signal, typically the last three sclks of the control word. the input source impedance (r source ) should be mini- mized to allow the t/h capacitance to charge within this allotted time. t acq = 11.5 (r source + r in ) c in where r source is the analog input source impedance, r in is 2.6k ? (which is the sum of the analog input mux and t/h switch resistances), and c in is 18pf (which is the sum of c t/h+ , c t/h- , and input stray capacitance). to minimize sampling errors with higher source imped- ances, connect a 100pf capacitor from the analog input to agnd. this input capacitor reduces the input? ac impedance but forms an rc filter with the source impedance, limiting the analog input bandwidth. for larger source impedance, use a buffer amplifier such as the max4430 to maintain analog input signal integrity. max1148 max1149 sclk din dout sstrb v dd v dd v dd v ss refadj com analog inputs ch4 ch5 ch6 ch7 ch0 ch1 ch2 ch3 ref agnd dgnd 0.01 f 0.1 f4.7 f 2.2 f p i/o i/o i/o sck mosi miso 10 ? shdn cs figure 4. typical application circuit max1149 analog input mux control logic internal clock input shift register output shift register +1.250v bandgap reference t/h dout sstrb v dd agnd sclk din com refadj ref ch6 ch7 ch4 ch5 ch1 ch2 ch3 ch0 dgnd sar adc ref clock in out 20k ? a v = 2.0v/v cs shdn figure 5. functional diagram
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs ______________________________________________________________________________________ 13 input bandwidth the max1146?ax1149 feature input tracking circuitry with a 3.0mhz small-signal bandwidth. the 3.0mhz input bandwidth makes it possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input protection internal protection diodes clamp the analog input to v dd and agnd. these diodes allow the analog inputs to swing from (agnd - 0.3v) to (v dd + 0.3v) without causing damage to the device. for accurate conver- sions, the inputs must not go more than 50mv below agnd or above v dd . note: if the analog input exceeds 50mv beyond the sup- ply rails, limit the current to 2ma. quick look use the circuit of figure 7 to quickly evaluate the max1148/max1149. the max1148/max1149 require a control byte to be written to din using sclk before each conversion. connecting din to v dd and clocking sclk feeds in a control byte of $ff hex (see table 1). trigger single-ended unipolar conversions on ch7 in external clock mode without powering down between conversions. in external clock mode, the sstrb output pulses high for two clock periods before the msb of the 14-bit conversion result is shifted out of dout. varying the analog input to ch7 alters the sequence of bits from dout. a total of 18 clock cycles are required per conversion (figure 10). all transitions of the sstrb and dout outputs occur on the falling edge of sclk. max1148 max1149 ch0 analog input mux ch1 ch2 ch3 ch4 ch5 ch6 ch7 com in+ in- track hold c t/h+ c t/h- track track ref 14-bit capacitive dac 14-bit capacitive dac ref hold hold figure 6. equivalent input circuit
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 14 ______________________________________________________________________________________ bit name description 7 (msb) start start bit. the first logic 1 bit after cs goes low defines the beginning of the control byte. 6 sel2 5 sel1 4 sel0 channel-select bits. the channel-select bits select which of the eight channels are used for the conversion (tables 2, 3, 4, and 5). 3 sgl/ dif 1 = single ended, 0 = differential. selects single-ended or differential conversions. in single-ended mode, input signal voltages are referred to com. in differential mode, the voltage difference between two channels is measured. 2 uni/ bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, connect com to agnd to perform conversion from 0 to v ref . in bipolar mode, connect com to v ref /2 to perform conversion from 0 to v ref . see table 7. 1 pd1 0 (lsb) pd0 selects clock and power-down modes. pd1 = 0 and pd0 = 0 selects full power-down mode*. pd1 = 0 and pd0 = 1 selects fast power-down mode*. pd1 = 1 and pd0 = 0 selects internal clock mode. pd1 = 1 and pd0 = 1 selects external clock mode. table 1. control byte format max1148 max1149 oscilloscope ch1 ch2 ch3 ch4 *full-scale analog input, conversion result = $fff hex sclk sstrb dout* dout sstrb sclk din v dd dgnd agnd com 0.01 f 0.01 f 2.2 f external clock ch7 refadj ref max1149 v ref = +2.500v max1148 v ref = +4.096v v ref a in v dd 10 ? 10 ? v com a in v ref shdn cs 0.1 f 4.7 f figure 7. quick-look circuit * the start bit resets power-down modes.
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs ______________________________________________________________________________________ 15 power-on reset when power is first applied, internal power-on reset cir- cuitry activates the max1146?ax1149 in internal clock mode, making the max1146?ax1149 ready to convert with sstrb high. no conversions should be performed until the power supply is stable. the first log- ical 1 on din with cs low is interpreted as a start bit. until a conversion takes place, dout shifts out zeros. starting a conversion start a conversion by clocking a control byte into din. with cs low, a rising edge on sclk latches a bit from din into the max1146?ax1149 internal shift register. after cs falls, the first logic 1 bit defines the control byte? msb. until this start bit arrives, any number of logic 0 bits can be clocked into din with no effect. table 1 shows the control-byte format. the max1146?ax1149 are compatible with spi/qspi and microwire devices. for spi, select the correct clock polarity and sampling edge in the spi control reg- isters. set cpol = 0 and cpha = 0. microwire, spi, and qspi transmit a byte and receive a byte at the same time. using the typical application circuit (figure 4), the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the 14-bit conversion result). sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com 000+ - 100 + - 001 + - 101 + - 010 + - 110 + - 011 +- 111 +- table 2. max1148/max1149 channel selection in single-ended mode (sgl/ dif = 1) sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 000+ - 001 +- 010 +- 011 +- 100 - + 101 - + 110 - + 111 -+ table 3. max1148/max1149 channel selection in differential mode (sgl/ dif = 0) sel2 sel1 sel0 ch0 ch1 ch2 ch3 com 000+ - 100 + - 001 + - 101 +- table 4. max1146/max1147 channel selection in single-ended mode (sgl/ dif = 1) sel2 sel1 sel0 ch0 ch1 ch2 ch3 000+ - 001 + - 100 -+ 101 -+ table 5. max1146/max1147 channel selection in differential mode (sgl/ dif = 0)
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 16 ______________________________________________________________________________________ digital output in unipolar input mode, the digital output is straight binary (figure 14). for bipolar input mode, the digital output is two? complement binary (figure 15). data is clocked out on the falling edge of sclk in msb-first format. clock modes the max1146?ax1149 can use either the external serial clock or the internal clock to drive the succes- sive-approximation conversion. the external clock shifts data in and out of the max1146?ax1149. external clock mode allows the fastest throughput rate (116ksps) and serial clock frequencies from 0.1mhz to 2.1mhz. internal clock mode provides the best noise performance because the digital interface can be idle during conversion. the internal clock mode serial clock frequency can range from 0 to 2.1mhz. internal clock mode allows the cpu to request a conversion and clock back the results. bits pd1 and pd0 of the control byte program the clock and power-down modes. the max1146?ax1149 power up in internal clock mode with all circuits activated. figures 8?1 illustrate the available clocking modes. external clock in external clock mode, the external clock not only shifts data in and out, but it also drives the analog-to- digital conversion. sstrb pulses high for two clock periods after the last bit of the control byte. successive- approximation bit decisions are made and the results appear at dout on each of the next 14 sclk falling edges (figures 8 and10). sstrb and dout go into a high-impedance state when cs is high. use internal clock mode if the serial clock frequency is less than 100khz or if serial clock interruptions could cause the conversion interval to exceed 140?. the conversion must complete in 140?, or droop on the t/h capacitors can degrade conversion results. internal clock when configured for internal clock mode, the max1146?ax1149 generate an internal conversion clock. this frees the ? from the burden of running the sar conversion clock and allows the conversion results to be read back at the processor? convenience, at any clock rate up to 2.1mhz. sstrb goes low at the start of the conversion and then goes high when the conver- sion is complete. sstrb is low for a maximum of 8.0?, during which time sclk should remain low for best noise performance. an internal register stores data when the conversion is in progress. sclk clocks the data out of this register at any time after the conversion is complete. after sstrb goes high, the second falling sclk clock edge produces the msb of the conversion at dout, followed by the remain- ing bits in msb-first format (figures 9 and 11). for the most accurate conversion, the max1146 max1149 digital i/o should remain inactive during the internal clock conversion interval (t conv ). do not pull cs high during conversion. pulling cs high aborts the current conversion. to ensure that the next start bit is recognized, clock in 18 zeros at din. when internal clock mode is selected, sstrb does not go into a high- impedance state when cs goes high. a rising edge on sstrb indicates that the max1146?ax1149 have fin- ished the conversion. the ? can then read the conver- sion results at its convenience. sclk sstrb din start sel2 sel1 sel0 pd1 pd0 high-z high-z 18916 24 input mux input t/h set according to previous control byte set to cb1 track track hold high-z dout t acq high-z t conv cb1 open reset to cb1 d13 d12 d11 d10 d9 d8 d6 d5 d4 d3 d2 d1 d0 d7 cs sgl/dif uni/bip figure 8. external clock mode?4 clocks/conversion timing
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs ______________________________________________________________________________________ 17 applications information idle mode the device is considered idle when all the bits have been clocked out or 18 zeros have been clocked in on din. start bit the falling edge of cs alone does not start a conver- sion. the first logic high clocked into din with cs low is interpreted as a start bit and defines the first bit of the control byte. the device begins to track on the fifth falling edge of sclk after a start bit has been recog- nized. a conversion starts on the eighth falling edge of sclk as the last bit of the control byte is being clocked in. the start bit is defined as follows: 1) the first high bit clocked into din with cs low any time the converter is idle. or 2) the first high bit clocked into din after bit 5 of a conversion in progress is clocked onto dout (figures 10 and 11). toggling cs before the current conversion is complete aborts the conversion and clears the output register. the fastest the max1146?ax1149 can run with cs held low between conversions is 18 clocks per conversion. figures 10 and 11 show the serial-interface timing neces- sary to perform a conversion every 18 sclk cycles. sclk sstrb din start sel2 sel1 sel0 pd1 pd0 18916 24 input mux input t/h set according to previous control byte set to cb1 track track hold high-z dout t acq high-z t conv cb1 open reset to cb1 d13 d12 d11 d10 d9 d8 d6 d5 d4 d3 d2 d1 d0 d7 cs sgl/dif uni/bip figure 9. internal clock mode timing?4 clocks/conversion timing sclk sstrb din start sel2 sel1 sel0 pd1 pd0 18 input mux input t/h set according to previous control byte track hold dout high-z 14 track 10 18 11 hold 14 d13 d12 10 d5 d4 11 set to cb2 set to cb1 start sel2 sel1 sel0 pd1 pd0 d13 d12 d5 d4 d3 d2 d1 d0 d3 d2 d1 d0 start sel2 sel1 sel0 15 hold cs cb1 cb2 t acq t conv t acq sgl/dif uni/bip uni/bip sgl/dif uni/bip sgl/dif figure 10. external clock mode18 clocks/conversion timing
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 18 ______________________________________________________________________________________ shutdown and power-down modes the max1146?ax1149 provide a hardware shutdown and two software power-down modes. pulling shdn low places the converter in hardware shutdown. the conversion is immediately terminated and the supply current is reduced to 300na. allow 2ms for the device to power-up when the internal reference buffer is used with c refadj = 0.01? and c ref = 2.2?. larger capacitors on c refadj and c ref increase the power-up time (table 6). no wake-up time is needed for the device to power-up from fast power- down when using an external reference. select a software power-down mode through the pd1 and pd0 bits of the control byte (table 1). when the conversion in progress is complete, software power- down is initiated. the serial interface remains active and the last conversion result can be clocked out. in full power-down mode, only the serial interface remains operational and the supply current is reduced to 300na. in fast power-down mode, only the bandgap reference and the serial interface remain operational, and the supply current is reduced to 600?. the max1146?ax1149 automatically wake up from software power-down when they receive the control byte? start bit (table 1). allow 2ms for the device to power-up when the internal reference buffer is used with c refadj = 0.01? and c ref = 2.2?. larger capacitors on c refadj and c ref increase the power- up time (table 6). no wake-up time is needed for the device to power-up from fast power-down when using an external reference. reference voltage the max1146?ax1149 can be used with an internal or external reference voltage. the reference voltage determines the adc input range. the reference deter- mines the full-scale output value (table 7). internal reference the max1146?ax1149 contain an internal 1.250v bandgap reference. this bandgap reference is connect- ed to refadj through a 20k ? resistor. bypass refadj with a 0.01? capacitor to agnd. the max1146/ max1148 reference buffer has a 3.277v/v gain to pro- vide +4.096v at ref. the max1147/max1149 reference buffer has a 2.000v/v gain to provide +2.500v at ref. bypass ref with a minimum 2.2? capacitor to agnd when using the internal reference. external reference an external reference can be applied to the max1146?ax1149 in two ways: 1) disable the internal reference buffer by connecting refadj to v dd and apply the external reference to ref (figure 12). 2) utilize the internal reference buffer by applying an external reference to refadj (figure 13). sclk sstrb din start sel2 sel1 sel0 pd1 pd0 18 input mux input t/h set according to previous control byte track hold t conv t conv dout high-z t acq 14 track d13 d12 10 18 d5 d4 d3 d2 d1 d0 11 hold 14 d13 d12 start 10 d5 d4 sel2 11 track cb1 cb2 set to cb2 set to cb1 reset to cb1 open reset to cb2 open cs start sel2 sel1 sel0 pd1 pd0 sgl/dif uni/bip sgl/dif uni/bip t acq figure 11. internal clock mode18 clocks/conversion timing c refadj * c ref power-up times from an extended power-down 0.01? 4.7? 2ms 0.1? 10? 25ms table 6. internal reference buffer power- up times vs. bypass capacitors * power-up times are dominated by c refadj .
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs ______________________________________________________________________________________ 19 method 1 allows the direct application of an external reference from 1.5v to v dd + 50mv. the ref input impedance is typically 10k ? . during conversion, an external reference at ref must deliver up to 210? and have an output impedance less than 10 ? . bypass ref with a 0.1? capacitor to agnd to improve its output impedance. method 2 utilizes the internal reference buffer to reduce the external reference load. the refadj input imped- ance is typically 20k ? . during a conversion, an external reference at refadj must deliver at least 100? and have an output impedance less than 100 ? . the max1146/max1148 reference buffer has a 3.277v/v gain and the max1147/max1149 has a gain of 2.000v/v. the external reference voltage at refadj multiplied by the reference buffer gain is the sar adc reference voltage. this reference appears at ref and must be from 1.5v to v dd + 50mv. bypass refadj with a 0.01? capacitor and bypass ref with a 2.2? capacitor to agnd. transfer function table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. output data coding for the max1146?ax1149 is bina- ry in unipolar mode and two? complement binary in bipolar mode with 1 lsb = (v ref /2 n ), where n is the number of bits (14). code transitions occur halfway between successive-integer lsb values. figure 14 and figure 15 show the input/output (i/o) transfer functions for unipolar and bipolar operations, respectively. serial interfaces the max1146?ax1149 feature a serial interface that is fully compatible with spi, qspi, and microwire. if a serial interface is available, establish the cpu? serial interface as a master, so that the cpu generates the serial clock for the adcs. select a clock frequency up to 2.1mhz. spi and microwire interface when using an spi (figure 16a) or microwire interface (figure 16b), set cpol = cpha = 0. two 8-bit readings are necessary to obtain the entire 14-bit result from the adc. dout data transitions on the serial clock? falling max1146 max1149 max6163 1.250v bandgap reference 20k ? sar adc ref reference buffer disabled dgnd v dd 0.1 f 0.1 f +5v out in gnd +5v 3.000v agnd refadj ref figure 12. external reference applied to ref max1146 max1149 0.047 f 510k ? 24k ? 100k ? +3.3v refadj figure 13. reference adjust circuit unipolar mode bipolar mode input and output modes zero scale full scale negative full scale zero scale positive full scale single-ended mode v com v ref + v com v com differential mode v in- v ref + v in- v in- table 7. full scale and zero scale note: the common mode range for the analog inputs is from agnd to v dd . ? + v v ref com 2 ? + ? v v ref in 2 + + v v ref com 2 + + ? v v ref in 2
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 20 ______________________________________________________________________________________ edge and is clocked into the ? on sclk? rising edge. the first 8-bit data stream contains the first 8-bits of dout starting with the msb. the second 8-bit data stream contains the remaining 6 result bits. qspi interface using the high-speed qspi interface (figure 17) with cpol = 0 and cpha = 0, the max1146?ax1149 sup- port a maximum f sclk of 2.1mhz. one 16-bit reading is necessary to obtain the entire 14-bit result from the adc. dout data transitions on the serial clock? falling edge and is clocked into the ? on sclk? rising edge. the first 14 bits are the data. pic16/pic17 ssp module interface the max1146?ax1149 are compatible with a pic16/pic17 microcontroller (?), using the synchro- nous serial-port (ssp) module. to establish spi com- munication, connect the controller as shown in figure 18 and configure the pic16/pic17 as system master. initialize the synchronous serial-port control register (sspcon) and synchronous serial-port status register (sspstat) to the bit patterns shown in tables 8 and 9. in spi mode, the pic16/pic17 ?s allow 8 bits of data to be synchronously transmitted and received simulta- neously. two consecutive 8-bit readings are necessary to obtain the entire 14-bit result from the adc. dout data transitions on the serial clock? falling edge and is clocked into the ? on sclk? rising edge. the first 8- bit data stream contains the first 8 data bits starting with the msb. the second data stream contains the remaining bits, d5 through d0. input voltage (lsb) binary output code (lsb) 0123 16383 v ref v ref 16381 0...000 0...001 0...010 0...011 1...111 1...110 1...101 1...100 1 lsb = v ref 16384 figure 14. unipolar transfer function input voltage (lsb) two's complement binary output code (lsb) 0123 8191 8192 8193 16383 v ref v ref 16381 1...000 1...001 1...010 1...011 1...111 0...000 0...001 0...111 0...110 0...101 0...100 1 lsb = v ref 16384 figure 15. bipolar transfer function sclk dout i/o sck miso v dd ss spi max1146 max1149 cs figure 16a. spi connections max1146 max1149 sclk dout i/o sk si microwire cs figure 16b. microwire connections
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs ______________________________________________________________________________________ 21 sclk dout cs sck miso v dd ss qspi max1146 max1149 cs figure 17. qspi connections sck sdi gnd gnd i/o sclk dout v dd v dd max1146 max1149 pic16/pic17 cs figure 18. spi interface connection for a pic16/pic17 controller control bit pici6/pici7 settings synchronous serial-port control register (sspcon) wcol bit 7 x write collision detection bit. sspov bit 6 x receive overflow detect bit. sspen bit 5 1 synchronous serial port enable bit: 0: disables serial port and configures these pins as i/o port pins. 1: e nab l es ser i al p or t and confi g ur es s c k, s d o, and s c i p i ns as ser i al - p or t p i ns. ckp bit 4 0 clock polarity select bit. ckp = 0 for spi master mode selection. sspm3 bit 3 0 sspm2 bit 2 0 sspm1 bit 1 0 sspm0 bit 0 1 synchronous serial port mode select bit. sets spi master mode and selects f clk = f osc / 16. table 8. detailed sspcon register content control bit max1146?ax1149 settings synchronous serial-port status register (sspstat) smp bit 7 0 spi data input sample phase. input data is sampled at the middle of the data output time. cke bit 6 1 spi clock edge select bit. data is transmitted on the rising edge of the serial clock. d/a bit 5 x data address bit. p bit 4 x stop bit. s bit 3 x start bit. r/w bit 2 x read/write bit information. ua bit 1 x update address. bf bit 0 x buffer full status bit. table 9. detailed sspstat register content
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 22 ______________________________________________________________________________________ tms32olc3x interface figure 19 shows an application circuit to interface the max1146?ax1149 to the tms320 in external clock mode. the timing diagram for this interface circuit is shown in figure 20. use the following steps to initiate a conversion in the max1146?ax1149 and to read the results: 1) the tms320 should be configured with clkx (transmit clock) as an active-high output clock and clkr (tms320 receive clock) as an active-high input clock. clkx and clkr on the tms320 are connected together with the max1146?ax1149 sclk input. 2) drive the cs of the max1146?ax1149 low through the xf_ i/o port of the tms320 to clock data into the max1146?ax1149 din. 3) write an 8-bit word (1xxxxx11) to the max1146?ax1149 to initiate a conversion and place the device into external clock mode. refer to table 1 to select the proper xxxxx bit values for your specific application. 4) the max1146?ax1149 sstrb output is moni- tored by the fsr input of the tms320. a falling edge on the sstrb output indicates that the con- version is in progress and data is ready to be received from the max1146?ax1149. 5) the tms320 reads in one data bit on each of the next 16 rising edges of sclk. these data bits rep- resent the 14-bit conversion result followed by 2 trailing bits, which should be ignored. 6) pull cs high to disable the max1146?ax1149 until the next conversion is initiated. layout, grounding, and bypassing careful pc board layout is essential for best system performance. boards should have separate analog and digital ground planes. ensure that digital and analog signals are separated from each other. do not run ana- log and digital (especially clock) lines parallel to one another, or digital lines underneath the device pack- age. figure 4 shows the recommended system ground con- nections. establish an analog ground point at agnd and a digital ground point at dgnd. connect all analog grounds to the star analog ground. connect the digital grounds to the star digital ground. connect the digital ground point to the analog ground point directly at the device. for lowest noise operation, the ground return to the star ground? power supply should be low imped- ance and as short as possible. max1146 max1149 xf clkx clkr dx dr fsr sclk din dout sstrb tms320lc3x cs figure 19. max1146?ax1149-to-tms320 serial interface sclk din sstrb dout start sel2 sel1 sel0 pd1 pd0 msb b12 b1 lsb high-z high-z cs sgl/dif uni/bip figure 20. tms320 serial-interface timing diagram
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs ______________________________________________________________________________________ 23 high-frequency noise in the v dd power supply degrades the device? high-speed performance. bypass the sup- ply to the digital ground with 0.1? and 4.7? capacitors. minimize capacitor lead lengths for best supply-noise rejection. connect a 10 ? resistor in series with the 0.1? capacitor to form a lowpass filter when the power supply is noisy. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the max1146?ax1149 are measured using the end-point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture definitions aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital sam- ples, signal-to-noise ratio (snr) is the ratio of full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog- to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to rms equivalent of all other adc output signals. sinad(db) = 20 x log (signalrms / noiserms) effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the full- scale range of the adc, calculate the enob as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component. chip information transistor count: 5589 process: bicmos thd vvvv v log = +++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 revision history pages changed at rev 2: 1, 20, 23, 25.
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs 24 ______________________________________________________________________________________ 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v dd sclk din ch3 ch1 ch0 top view sstrb dout dgnd agnd n.c. n.c. n.c. n.c. 12 11 9 10 refadj ref com max1146 max1147 tssop shdn cs 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v dd sclk din ch3 ch2 ch1 ch0 sstrb dout dgnd agnd ch7 ch6 ch5 ch4 12 11 9 10 refadj ref com max1148 max1149 tssop shdn cs ch2 pin configurations
max1146?ax1149 multichannel, true-differential, serial, 14-bit adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 2007 maxim integrated products is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) tssop4.40mm.eps package outline, tssop 4.40mm body 21-0066 1 1 i
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > a nalog-to-digital c onverters max1146, max1147, max1148, max1149 multichannel, true-differential, serial, 14-bit adc s quickview technical documents ordering info more information all note: this product requires use of the following: max1149 evkit software ordering information notes: other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 1. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 2. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 3. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 4. devices: 1-30 of 30 m ax1146 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max1146bc up tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * 0c to +70c rohs/lead-free: no materials analysis max1146bc up+t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * 0c to +70c rohs/lead-free: lead free materials analysis max1146bc up+ tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * 0c to +70c rohs/lead-free: lead free materials analysis max1146bc up-t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * 0c to +70c rohs/lead-free: no materials analysis max1146beup-t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * -40c to +85c rohs/lead-free: no materials analysis max1146beup tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * -40c to +85c rohs/lead-free: no materials analysis m ax1147 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max1147bc up tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * 0c to +70c rohs/lead-free: no materials analysis max1147bc up+t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * 0c to +70c rohs/lead-free: lead free materials analysis max1147bc up+ tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * 0c to +70c rohs/lead-free: lead free materials analysis max1147bc up-t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * 0c to +70c rohs/lead-free: no materials analysis
max1147beup+ tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * -40c to +85c rohs/lead-free: lead free materials analysis max1147beup+t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * -40c to +85c rohs/lead-free: lead free materials analysis max1147beup tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * -40c to +85c rohs/lead-free: no materials analysis max1147beup-t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * -40c to +85c rohs/lead-free: no materials analysis m ax1148 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max1148bc up-t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * 0c to +70c rohs/lead-free: no materials analysis max1148bc up+t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * 0c to +70c rohs/lead-free: lead free materials analysis max1148bc up+ tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * 0c to +70c rohs/lead-free: lead free materials analysis max1148bc up tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * 0c to +70c rohs/lead-free: no materials analysis max1148beup+t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * -40c to +85c rohs/lead-free: lead free materials analysis max1148beup tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * -40c to +85c rohs/lead-free: no materials analysis max1148beup+ tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * -40c to +85c rohs/lead-free: lead free materials analysis max1148beup-t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * -40c to +85c rohs/lead-free: no materials analysis m ax1149 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max1149bc up+t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * 0c to +70c rohs/lead-free: lead free materials analysis max1149bc up-t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * 0c to +70c rohs/lead-free: no materials analysis max1149bc up tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * 0c to +70c rohs/lead-free: no materials analysis max1149bc up+ tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * 0c to +70c rohs/lead-free: lead free materials analysis max1149beup+ tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * -40c to +85c rohs/lead-free: lead free materials analysis max1149beup-t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * -40c to +85c rohs/lead-free: no materials analysis max1149beup tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-3 * -40c to +85c rohs/lead-free: no materials analysis max1149beup+t tssop;20 pin;43 mm dwg: 21-0066i (pdf) use pkgcode/variation: u20+3 * -40c to +85c rohs/lead-free: lead free materials analysis
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